The present invention relates generally to asynchronous memory architectures, and more specifically to an architecture for a low power, high density (smaller area) asynchronous memory.
In the past, low power asynchronous dual port memories were designed utilizing a nine transistor (9-T) core cell architecture shown in FIG. 1. In such core cells 100, the write and read were both single ended. Consequently, the value to be written to the cell 100 is driven from the Write Bitline (WBL) 102 into the cell when Write Wordline (WWL) 104 and Local Write Enable (LWEL) 112 are turned on. Similarly, when the Read Wordline (RWL) 106 is turned ON, the inverter driver 108 drives the Read Bitline (RBL) 110 either low (i.e., xe2x80x9c0xe2x80x9d) or high (i.e., xe2x80x9cVDDxe2x80x94Vtnxe2x80x9d) depending on the stored value in the cell 100.
Writing low in the 9-T core cell 100 shown in FIG. 1 may be accomplished without difficulty. However, writing high in the 9-T cell 100 is problematic since such cells 100 are very sensitive to low voltage margin To compensate for this problem, a twelve transistor (12-T) core cell architecture was developed. This architecture is illustrated in FIG. 2. In such a 12-T core cell architecture, a pseudo-double ended write is done when high (i.e., xe2x80x9c1xe2x80x9d) is written to the cell 200. The back-to-back inverters 202 and 204 inside the cell 200 are generally skewed so that the feedback inverter 202 is slightly weaker and the forward inverter 204 is stronger.
In the architectures illustrated in FIGS. 1 and 2, the Local Write Enable (LWEL) signals 112 (FIG. 1) and 206 (FIG. 2) are used to turn OFF the columns (when the memory contains more than one column per bit). This is to avoid writing into the columns which are not active since the global Write Wordline (WWL) 104 (FIG. 1) and 208 (FIG. 2) is active. It can be seen that since the 9-T and 12-T cell architectures utilize either 9 or 12 transistors, the core cell size turns out to be very large. Moreover, the low voltage margin may still be a problem depending on the process used (for example, if the process is skewed in such a way that it makes the forward inverter p-channel stronger than desired so that writing high (i.e., xe2x80x9c1xe2x80x9d) becomes more difficult). Process tolerances may also lead to differences in transistor sizes leading to difficulty in writing xe2x80x9c1xe2x80x9d into the cell.
Accordingly, the present invention is directed to an architecture for a low power, high density (smaller area) asynchronous memory employing a double ended write into the core memory cells. In an exemplary embodiment, the memory cell includes a forward inverter and a feedback inverter disposed in a back-to-back arrangement (i.e., back-to-back inverters). The memory cell further includes two write access transistors, a read inverter, and a read access transistor. Write Bit Lines coupled to write access transistors are precharged to Vddxe2x88x92Vtn, or, alternately Vdd, when the signal Write Enable (WE) is low (i.e., xe2x80x9c0xe2x80x9d). When the signal Write Enable (WE) goes high, the Write Bit Lines of columns within the memory that are not being accessed may be left floating so that they may perform an unintended read. However, there are no unintended writes into the cell. On columns where writes are performed, the Write Bit Lines are driven to Vdd or Vss. Accordingly, the Local Write Enable (LWEL) signal and three (3) transistors of conventional 12-T memory cells such as memory cell 200 shown in FIG. 2 are eliminated by the present invention thereby providing higher bit density.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention as claimed. The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate presently preferred embodiments of the invention, and together with the general description given above and the detailed description of the preferred embodiments given below, serve to explain the principles of the invention.